1. Field of the Invention
The present invention is generally related to a structure of a flash memory and a manufacturing method thereof. More particularly, the present invention relates to a structure of a flash memory having a conductive spacer in floating gate and a manufacturing method thereof.
2. Description of the Related Art
A memory device is a semiconductor device for storing data or information. In recent years, as the performance of the microprocessor of the computer has become more and more better, and the volume of software program execution and operation requires to be correspondingly huge, and the storage capacity requirement of the memory device also needs to be correspondingly increased. In order to manufacture a high density and low-cost memory device with a view to satisfy the requirement of the continual development of computers, the development of the manufacturing technology and process of memory device has become a driving force for developing a highly integrated semiconductor device.
For example, a flash memory device has become a widely preferred non-volatile memory device in a personal computer and electronic device because flash memory can be repeatedly used for saving, reading and erasing data, and the data stored in the memory can also be preserved even when the electrical power is cut off.
In a typical flash memory device, the floating gate and the control gate are formed using a doped polysilicon. Moreover, an inter-poly dielectric is disposed between the floating gate and the control gate, and a tunnel oxide layer is disposed between the floating gate and the substrate. To subject a flash memory to data write/erase operation, usually a bias is applied between the control gate and the source/drain region to inject electrons into the floating gate or to pull out electrons from the floating gate. To read out data from the flash memory, an operation voltage is applied to the control gate. The charged state of the floating gate will effect the on/off states of the channel, and the level 0 and 1 of the data read from the flash memory is dependent on the on/off states of the channel.
Referring FIGS. 1 and 2, FIG. 1 is a top view illustrating a conventional flash memory, and FIG. 2 is a cross-sectional view taken along the line A-A′ of the flash memory of FIG. 1. The flash memory includes a substrate 100, a tunnel oxide layer 104, a floating gate 106, an inter-poly dielectric 108 and a control gate 110. A plurality of shallow trench isolation (“STI”) layer 102 is formed in the substrate 100 to isolate each memory cell. The floating gate 106 has a shape similar to a rectangular block, and forms on the tunnel oxide layer 104 disposed on the substrate 100. The control gate 110 has a shape similar to a bar, and the alignment of the control gate 110 is perpendicular to the STI layer 102 to isolate the inter-poly dielectric 108 disposed on the floating gate 106 and the substrate 100. After the floating gate 106 and the control gate 110 is formed, the substrate 100 is doped to form a source region 112 and a drain region 114.
However, in the marked (circled) region 116 of FIG. 1 and FIG. 2, the contour of the floating gate 106 is similar to a right angle since the shape of the floating gate 106 is similar to a rectangular block in the above flash memory. Therefore, when the flash memory is operated and the applied voltage on the control gate 110 is increased, the charge stored in the floating gate 106 may penetrate into the control gate 110 from the marked (circled) region 116 through the inter-poly dielectric 108, and then the stored data is leaked out. In addition, during the etching process of the floating gate, if the etching condition is not well controlled, an undercut may occur in the side walls of the floating gate, shape of the corners of the floating gate more sharp, and thereby allowing the penetration of the charge of the stored data much more easier.